1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM, hereinafter) requiring refresh operation which is an operation for recharging electric charge periodically so as to retain electric charge accumulated in a memory cell, and more particularly, to a semiconductor memory device in which power consumption in the dormant state where only the recharging is carried out can be reduced, thereby to be able to use for a long time when installed in various portable equipments.
2. Description of Related Art
In recent years, many high-speed memories having large capacities are mounted in various portable equipments such as a notebook personal computer and a mobile personal computer as functionality is advancing. The DRAM is a typical memory, and is used as a standard memory of the portable equipment because of its large capacity and high speed.
On the other hand, the portable equipment itself is required to operate for a long time with one charge and is required that the power consumption of its components is small. In the case of the DRAM, it is necessary to periodically refresh for retaining electric charge accumulated in its memory cell, and to recharge the electric charge accumulated in the memory cell, and electric power is consumed even in the dormant state where data are not input or output. Therefore, in order to reduce the power consumption of the portable equipment, it is also necessary to reduce the power consumption at the time of refresh operation of the DRAM.
So as to meet the above requirement, in the DRAM, a refresh operation for reducing the power consumption in a so-called data retention mode in the dormant state is carried out. The data retention mode will be explained below with reference to FIGS. 38 to 43.
FIG. 38 shows a circuit block diagram 300 of a DRAM. A control circuit 301 receives external signals such as /RAS (Row Address Strobe) signal, /CAS (Column Address Strobe) signal, /WE (Write Enable) signal, CLK (Clock) signal, /CS (Chip Select) signal and the like, and controls input of address, input and output of data, refresh control and the like. A column decoder 302 connects a bit line (BL) selected by a column address (CA) to a data bus (not shown), thereby inputting and outputting data. An internal reduced voltage generating circuit 303 is mounted in the DRAM for reducing an external power supply voltage when mismatch is generated between an external power supply voltage and a power supply voltage required for a device as the packing density is increased. A substrate voltage generating circuit 304 is a circuit for generating voltage for biasing a substrate portion in a memory cell array 305 to negative voltage because of a reason which will be mentioned later.
In the DRAM, a memory cell group is disposed on the memory cell array 305 in a matrix manner, and a large number of memory cells are connected to a word line (WL in the drawing) selected in correspondence with a row address signal. This memory cell array 305 comprises six, for example, blocks BLK1 to BLK6. At the time of the refresh operation, row address (RAref) to be refreshed by a refresh address counter circuit 307 is counted up based on a refresh cycle set by a refresh timer circuit 306, and is supplied to a row address selecting circuit 308. The row address selecting circuit 308 selects the refresh row address (RAref), a part of the refresh row address (RAref) is supplied to a cell array block selecting circuit 309, and the remainder is supplied to a word line selecting circuit 310. A word line driving circuit 311 activates a word line in the block corresponding to the refresh address (RAref) in response to outputs of the cell array block selecting circuit 309 and the word line selecting circuit 310.
Electric charge in a memory cell connected to the selected word line WL is read out to the bit line BL, and is amplified by a sense amplifier (not shown) so that the amount of electric charge accumulated in the memory cell is restored. This refresh operation is carried out by selecting the word lines WL in sequence within a time period during which the electric charge in the memory cell is retained in the memory cell.
FIG. 39 schematically shows the positional relation among the memory cell 313, the word lines WL and bit lines BL (BL1, /BL1, /BL2 in FIG. 39) in the memory cell array 305. FIG. 39 shows a region B in FIG. 38 in enlarged scale. In FIG. 39, symbols .largecircle. represent memory cells 313. A memory cell group intersecting the word line WL is selected by the word line WL, and electric charge is input and output on the intersecting bit lines BL (BL1, /BL1, /BL2 in FIG. 39). The memory cells 313 are laid out in a staggered arrangement manner, and the positional relation among the memory cells 313 including the word lines WL, bit lines BL (BL1, /BL1, /BL2 in FIG. 39) and the like is most densely integrated.
A cross section structure of the memory cell 313 along the bit line BL1 in FIG. 39 is shown in FIG. 40. Each of M1 and M2 of the memory cell 313 comprises one NMOS transistor 315 formed on a P-type substrate 314 and one cell capacitor 316, surroundings thereof are separated from adjacent cells by thick field oxide layers 317. The adjacent cells are disposed in a back-to-back manner through the field oxide layers 317, and WL2 of the word line WL which selects memory cells 313 which are adjacent in the vertical direction in FIG. 40 are disposed on the field oxide layers 317. In the memory cell 313 of this structure, electric charge as the data is accumulated in the cell capacitor 316, and the input and output as well as the retention of the electric charge are conducted by switching the NMOS transistor 315.
In recent years, when a substrate is grounded, a threshold voltage of the NMOS transistor is about 0.4 V due to the progression of packing density, but with such a low threshold voltage, the amount of accumulated electric charge is reduced by a leak current from the cell capacitor 316 through the switching NMOS transistor 315 of the memory cell 313, and it is not preferable in terms of electric charge retention characteristics in some cases. Further, due to a structure in view of a layout of the memory cell 313, the NMOS transistor (field MOS transistor, hereinafter, MF1 in FIGS. 39 and 40) is formed such that diffusion layers of the adjacent cell capacitors 316 sandwiches the field oxide layer 317, and the WL2 of the word line WL on the field oxide layer 317 is used as a gate. Due to the progression of packing density, a threshold voltage of the field MOS transistor MF1 tends to be shallower, and in a state where the substrate has grounded potential, the current leak (leak current (2) in FIG. 40) between the adjacent cell capacitors 316 by driving of WL2 of other word line WL may induce some problems, and this is known as a so-called disturb problem. To solve the above problem, in recent DRAM, threshold voltage of the switching NMOS transistor 315 and the field MOS transistor MF1 are set deep utilizing a substrate bias effect of the MOS transistor by biasing negative voltage VBB to the substrate 314, thereby preventing the leak current and the like.
Here, the purpose of the refresh operation is achieved by amplifying the electric charge of the cell capacitor 316 read out on a bit line BL without inputting or outputting data, and again charging the electric charge to the cell capacitor. Concerning the frequency of this operation, the operation cycle may be set long within a range of produce specification in accordance with the electric charge retention ability of the memory cell 313, and unlike the normal data input and output operation requiring high access speed, high speed of the operation is not required.
That is, in the refresh operation, the power supply voltage can be reduced and as a result, voltage applied to the word line WL can also be reduced. Therefore, even if the substrate bias effect is weakened, the disturb problem can be improved, and the leak current (2) in FIG. 40 can be reduced. In addition, the VBB voltage is increased in the negative voltage (which is expressed as "VBB is shallow", hereinafter), to weaken the substrate bias effect. Therefore, electric field applied to a junction between the substrate and the diffusion layer of the cell capacitor 316 of the memory cell 313 is also relaxed and thus, the leak current (3) in the connected portion in FIG. 40 can also be reduced. The reduction in the substrate bias effect in this case is so small that the leak current (the leak current (1) in FIG. 40) through the NMOS switch 315 does not induce any problem.
FIG. 43 is a graph schematically showing that the amount of accumulated electric charge is reduced with time after the cell capacitor 316 is charged at time t=0. In FIG. 43, axis of ordinates shows the amount of accumulated electric charge, and axis of abscissas shows time. Symbol A represents a process of reduction in the accumulated electric charge in a normal operation state, and symbol C represents a process of the reduction in the accumulated electric charge in the above-described state where the power supply voltage is reduced. Both the cases are based on the assumption that the leak current is constant, therefore the amount of accumulated electric charge is reduced linearly (symbol B will be described later). As shown in FIG. 43, the reducing speed of the amount of the accumulated electric charge of the memory cell 313 in the symbol C is reduced as compared with the speed in the normal operation state, and the time (tref in FIG. 43) during which the amount of the electric charge (Qcrit) is reduced to a level requiring recharge by the refresh operation is longer than the time of the normal operation state(tn in FIG. 43). Therefore, the interval of refresh operations can be set long.
By applying the above operation to the refresh operation in dormant state, the power supply voltage VDD can be reduced, and the cycle of the refresh operation can be set long. Therefore, the current consumption can be reduced, and the power consumption which is the product of the power supply voltage and the cycle can be reduced with the square effect. The present operation is employed as a technique indispensable for DRAM mounted in the portable equipment as the data retention mode.
However, in the above-described conventional data retention mode, due to unbalanced transient voltage value between the substrate voltage VBB and the power supply voltage VDD applied to the memory cell, or between the substrate voltage VBB and an internal voltage Vint which is reduced in a chip, when an operation mode shifted to the data retention mode or when the operation mode is shifted back from the data retention mode, there is a problem that power consumption can not be a reduced sufficiently in the data retention mode. In addition, there is a problem that the electric charge decays when the operation mode is returned from the data retention mode.
The above problems will be explained based on FIGS. 41 to 43. FIG. 41 schematically shows one example of a chip layout 318 of the DRAM. The memory cell array 305 is divided into six cell array blocks (BLK1 to BLK6) for the sake of expediency, and the cell array blocks are disposed on a chip 318. As shown in FIG. 41, the memory cell array 305 occupies a large area on the chip 318. On the other hand, the substrate voltage generating circuit 304 generates and supplies VBB voltage for biasing a substrate of the memory cell array 305, but the substrate region 314 constitutes a substrate capacity component 319 having large area and large capacity (FIG. 38), whereas a driving ability of this circuit is limited due to constraints of an area to be occupied by the substrate voltage generating circuit 304 on the chip 318. Therefore, the transient response characteristics of the generated VBB are limited, and the following ability with respect to abrupt variation in the substrate voltage has a certain limit.
Therefore, as shown in FIG. 42A, if the power supply voltage VDD or the internal voltage Vint is reduced by shifting the operation mode to the data retention mode, a set value of the substrate voltage generating circuit 304 is changed such that the substrate voltage VBB in accordance with these power supply voltages is output, but since the ability for positively discharging the electric charge accumulated in the substrate capacity component 319 of the memory cell array 305 is limited, a certain transient period is required until the substrate potential VBB is converged to a new set voltage (a region B in FIG. 42A).
In such a transient period, even though the power supply voltage (VDD or Vint) is reduced, a state where the VBB is low in negative voltage (this will be explained as "VBB is deep", hereinafter) is continued, both the voltages are out of proportion to each other. That is, since the power supply voltage is applied to the cell capacitor 316 of the memory cell 313 and the electric charge is accumulated, the amount of the electric charge which can be accumulated in the cell capacitor 316 is reduced due to the reduction of the power supply voltage. Therefore, the substrate voltage VBB to be applied between the diffusion layer which is an electric charge accumulation layer of the cell capacitor 316 and the substrate 314 is kept deep during this transient period, the electric field applied to the junction is large and thus, the leak current (leak current (3) in FIG. 40) is large. Symbol B in FIG. 43 shows this state. The leak current is the greatest immediately after the power supply voltage VBB is reduced and thereafter, as the time is elapsed, the substrate voltage VBB becomes shallower as the substrate voltage VBB is converged to a new set value after the power supply voltage is reduced. Therefore, elapsed time of the accumulated electric charge amount is represented as a curved line curving downward. As can be seen from FIG. 43 also, there is an unbalanced state where the leak current is large as compared with the accumulated electric charge amount, the reducing speed of the accumulated electric charge amount is faster than that in the normal operating state after the power supply voltage reduces (symbol C in FIG. 43), and in some cases, the state is worsened as compared with the normal operating state before the power supply voltage is reduced (symbol A in FIG. 43), and the retention ability of electric charge is worsened.
Therefore, even though proficiency of the refresh period in the data retention mode is higher than that in the normal operating state, and even though the data retention mode has ability for setting the refresh interval longer, the retention characteristic of the accumulated electric charge of the memory cell 313 is worsened due to delay of transient response of VBB in the shifting period to this mode, the cycle of the refresh operation must be set short. That is, after the operation mode is shifted to the data retention mode, the refresh operation must be carried out while keeping the short cycle, the current consumption in this mode remains great against the initial purpose, the power consumption can only be reduced in an amount corresponding to the reduction of the power supply voltage, and there is a problem that the power consumption can not be reduced sufficiently.
Further, as shown in FIG. 42B, if the power supply voltage VDD or the internal voltage Vint is increased because the operation mode is returned from the data retention mode, the set value of the substrate voltage generating circuit 304 is changed such that the substrate voltage VBB in accordance with the power supply voltage is output, but due to the limit of ability for charging the electric charge accumulated in the substrate capacity component 319 of the memory cell array 305, a certain transient period is required until the substrate voltage VBB is converged to a new set voltage.
During the transient period, even though the power supply voltage (VDD or Vint) is high, a state where the substrate voltage VBB is shallow is continued, and both the voltages are out of balance. During this time, when the word line WL passing between the cell capacitors 316 of the adjacent memory cells 313 is continuously selected and is retained in high voltage, if the electric charge of the adjacent cell capacitors 316 is combination of high level and low level, leak current (leak current (2) in FIG. 40) by the effect of the field MOS transistor MF1 is generated between the diffusion layers of the cell capacitors 316 sandwiching the word line WL, the high level side accumulated electric charge leaks toward the low level side diffusion layer, there is an adverse possibility that the electric charge decays, and a so-called disturb problem is caused.
Furthermore, in an operation state other than the above-described state, in case that the power supply voltage VDD, the internal voltage Vint or the substrate voltage VBB is varied and these voltages are out of balance, there is a problem that the electric charge retention characteristic of the memory cell 313 is worsened by the same reason, and the electric charge decays.